----------------------------------------------------------------------------------------------------------------------------------
--		Riccar/TEAL Logic Simulation
--
-- Primary calculator logic, environment-independant.
-- Clock, keyboard & displays are external.
--
-- 2021 Apr / bh
-- 2026 Okt: korrigiert nach Schaltplan Rendition 2021 Sep 10, Stellen mit "KORR:" markiert
--
----------------------------------------------------------------------------------------------------------------------------------


----------------------------------------------------------------------------------------------------------------------------------
-- Timing
----------------------------------------------------------------------------------------------------------------------------------
-- bit timing

FFDCT		ØB4~			d<ØB2~		c<ØC		t<ØT
FFDCT		ØB8			d<ØB4		c<ØC		t<ØT
FFDCT		ØB1			d<ØB8		c<ØC		t<ØT

NANDN		ØB2~			<ØB4		<ØB8		<ØB1

------------------------------------------------------------
-- digit timing
-- break out flip-flops into separate c/t gated types to simulate M5812 ICs.

-------------
-- UK5

NOT				UK5.1		<UL1.9

FFD/gate=0			ØD15c		d<UK5.1		g<ØB4~
FFD/gate=0			ØD15~		d<ØD15c		g<ØB1~

FFD/gate=0			ØD16c		d<ØD15~		g<ØB4~
FFD/gate=0			ØD16~		d<ØD16c		g<ØB1~

FFD/gate=0			ØD0c		d<ØD16~		g<ØB4~
FFD/gate=0			ØD0~		d<ØD0c		g<ØB1~

FFD/gate=0			ØD1c		d<ØD0~		g<ØB4~
FFD/gate=0			ØD1~		d<ØD1c		g<ØB1~

FFD/gate=0			ØD2c		d<ØD1~		g<ØB4~
FFD/gate=0			ØD2~		d<ØD2c		g<ØB1~

FFD/gate=0			ØD3c		d<ØD2~		g<ØB4~
FFD/gate=0			ØD3~		d<ØD3c		g<ØB1~

AND				UK5.6		<ØD15c	<ØD16c	<ØD0c	<ØD1c	<ØD2c	<ØD3c	<MA207

-------------
-- UL1

FFD/gate=0			ØD4c		d<ØD3~		g<ØB4~
FFD/gate=0			ØD4~		d<ØD4c		g<ØB1~

FFD/gate=0			ØD5c		d<ØD4~		g<ØB4~
FFD/gate=0			ØD5~		d<ØD5c		g<ØB1~

FFD/gate=0			ØD6c		d<ØD5~		g<ØB4~
FFD/gate=0			ØD6~		d<ØD6c		g<ØB1~

FFD/gate=0			ØD7c		d<ØD6~		g<ØB4~
FFD/gate=0			ØD7~		d<ØD7c		g<ØB1~

FFD/gate=0			ØD8c		d<ØD7~		g<ØB4~
FFD/gate=0			ØD8~		d<ØD8c		g<ØB1~

FFD/gate=0			ØD9c		d<ØD8~		g<ØB4~
FFD/gate=0			ØD9~		d<ØD9c		g<ØB1~

AND				UL1.6		<ØD4c	<ØD5c	<ØD6c	<ØD7c	<ØD8c	<ØD9c	<UK5.6
-- KORR: Freigabe wieder mit ØB1~ wie im Original und Schaltplan S.6 (UL1 ACT an ØT=ØB1~).
--       Mit g<ØB1 schwingt der Digit-Ringzähler während ØB4.
FFD/gate=0			UL1.9		d<UL1.6		g<ØB1~

--------------
-- UK1

FFD/gate=0			ØD10c		d<ØD9~		g<ØB4~
FFD/gate=0			ØD10~		d<ØD10c		g<ØB1~

FFD/gate=0			ØD11c		d<ØD10~		g<ØB4~
FFD/gate=0			ØD11~		d<ØD11c		g<ØB1~

FFD/gate=0			ØD12c		d<ØD11~		g<ØB4~
FFD/gate=0			ØD12~		d<ØD12c		g<ØB1~

FFD/gate=0			ØD13c		d<ØD12~		g<ØB4~
FFD/gate=0			ØD13~		d<ØD13c		g<ØB1~

AND				MA207		<ØD9~	<ØD10~	<ØD11~	<ØD12~	<ØD13~

-----------------------------------------------------------------
-- misc timing

NANDN		ØEOD~			<ØC		<ØB8~
NANDN		ØEON~			<ØEOD~		<ØD16~


----------------------------------------------------------------------------------------------------------------------------------
-- Keyboard
----------------------------------------------------------------------------------------------------------------------------------
-- numerals

NORN		MA204			<K1~		<K3~		<K5~		<K7~		<K9~
NORN		MA203			<K2~		<K3~		<K6~		<K7~
NORN		MA202			<K4~		<K5~		<K6~		<K7~
NORN		GD241			<K8~		<K9~

NANDN		GD245			<ØB1~		<MA204
NANDN		GD247			<ØB2~		<MA203
NANDN		GD248			<ØB4~		<MA202
NANDN		GD246			<ØB8~		<GD241

NORN		MA206			<GD245		<GD247		<GD248		<GD246
NANDN		KNUM~			<ØD0~		<MA206

NORN		MA205			<GD241		<MA202		<MA203		<MA204		<K0~
FFDCT		KPN~			d<MA205		c<ØEON~		t<ØT


-----------------------------------------------------------------
-- KPD flag

FFDCT		KPD~			d<KP~		c<ØEON~		t<ØT


-----------------------------------------------------------------
-- KPR flag

FFDCT		KPR~			d<KR~		c<ØEON~		t<ØT


-----------------------------------------------------------------
-- Clear

NORN		KC~			<KKC~		<POC~


-----------------------------------------------------------------
-- K function combinations

NORN		KE~			<KEA~		<KES~
NORN		KASC~			<KA~		<KS~		<KC~
NORN		KASMDC~			<KM~		<KD~		<KASC~
NORN		KASMDCE~		<KASMDC~	<KE~
NOT		KASMDCE			<KASMDCE~

NORN		KASCE~			<KASC~		<KE~


-----------------------------------------------------------------
-- KPO flag

	-- *** HACK ! ***  simulate capacitor in trigger with edge-triggered FF,
	-- KPO to be cleared in ST15 before returning to ST11 idle,
	-- after DP aligned in ST34,
	-- and in ST11 if not OPE (no need to assert KPO as we stay in ST11)
NANDN		kpo34~			<ST34~		<FDPAL~
NANDN		kpo11~			<ST11~		<OPE
ORN		kpoClr			<ST15~		<kpo34~		<kpo11~
FFD/+/r		kpoD			k<KASMDCE	d<HIGH		r<kpoClr

FFDCT		KPO~			d<kpoD~		c<ØEON~		t<ØT


-----------------------------------------------------------------
-- OP flags

	-- *** HACK ! ***  delay in triggering, done by cap delay in physical, accomplished by 2 ØD delay
SRCT/bits=2	delayKASCE~		d<KASCE~	c<ØB4~		t<ØB1~
SRCT/bits=2	delayKM~		d<KM~		c<ØB4~		t<ØB1~
SRCT/bits=2	delayKD~		d<KD~		c<ØB4~		t<ØB1~

NANDN		GD208			<KASMDCE	<FKOP		<ST11~
NANDN		GMA201.4		<GD208		<delayKASCE~
NANDN		GMA201.3		<GD208		<delayKM~
NANDN		GMA201.2		<GD208		<delayKD~

ORN		OPMD~			<OPAS~		<KS~		<GMA201.4	<POC~	
ORN		OPAS~			<OPMD~		<GMA201.2	<GMA201.3

ORN		OPSD~			<OPAM~		<GMA201.4	<GMA201.3	<POC~
ORN		OPAM~			<OPSD~		<GMA201.2	<KS~	

NANDN		OPM~			<OPAM~		<OPMD~
NANDN		OPD~			<OPSD~		<OPMD~


-----------------------------------------------------------------
-- OPE flags

NORN		GD229			<OPE~		<KE~
NOT		KASMDC			<KASMDC~
FFDCT/s		OPE~			d<GD229		c<ØC		t<ØT		s<KASMDC

ORN		OPES~			<OPEA~		<ST11~		<KEA~
ORN		OPEA~			<OPES~		<KES~		<ST12~  <POC~	-- Hinweis: POC~ nicht im Schaltplan, Initialisierungshilfe

-- Use buffer rather than synonym to keep op name in display
BUFFER		BNENT~			<OPEA~


----------------------------------------------------------------------------------------------------------------------------------
-- State Machine
----------------------------------------------------------------------------------------------------------------------------------
-- ST register

FFDCT		ST11~			d<NST11~	c<GD17		t<ØT
FFDCT		ST12~			d<NST12~	c<GD17		t<ØT
FFDCT		ST13~			d<NST13~	c<GD17		t<ØT
FFDCT		ST14~			d<NST14~	c<GD17		t<ØT
FFDCT		ST15~			d<NST15~	c<GD17		t<ØT

FFDCT		ST21~			d<NST21~	c<GD17		t<ØT
FFDCT		ST22~			d<NST22~	c<GD17		t<ØT
FFDCT		ST23~			d<NST23~	c<GD17		t<ØT
FFDCT		ST24ff~			d<NST24~	c<GD17		t<ØT
FFDCT		ST25ff~			d<NST25~	c<GD17		t<ØT

FFDCT		ST31~			d<NST31~	c<GD17		t<ØT
FFDCT		ST32~			d<NST32~	c<GD17		t<ØT
FFDCT		ST33~			d<NST33~	c<GD17		t<ØT
FFDCT		ST34ff~			d<NST34~	c<GD17		t<ØT
FFDCT		ST35~			d<NST35~	c<GD17		t<ØT

NORN		GMRQ~			<NST11~ <NST12~ <NST13~ <NST14~ <NST15~    <NST21~ <NST22~ <NST23~ <NST24~ <NST25~    <NST31~  <NST32~ <NST33~ <NST34~ <NST35~
NANDN		GD17			<ØEON~		<GMRQ~

-- do state suppression with gates, doesn't work with Set on FF with sequential 13,23 suppression
NANDN		ST24~			<ST24ff~	<STSUP
NANDN		ST25~			<ST25ff~	<STSUP
NANDN		ST34~			<ST34ff~	<STSUP

NORN		STAC~			<ST12~		<ST14~		<ST33~		<ST35~		<ST32~		<ST34~

NORN		ST11+31+33~		<ST11~		<ST31~		<ST33~


-----------------------------------------------------------------
-- state suppression

ORN		STSUP			<ST13~		<ST23~		<ST32~		<KPR~


-----------------------------------------------------------------
-- next state

-- 11
NANDN		MO8			<ST35~		<KPR~		<ERR
NORN		NST11~			<MO8		<KC~		<ST15~

-- 12
NANDN		GD9			<BNENT~		<KPD~
NANDN		MO9			<ST35~		<BNENT~		<KPN~
NANDN		GD3			<BNENT~		<KPN~
NANDN		GD8			<OPAS~		<GD4
NANDN		GD4			<ST11~		<KPO~		<OPE~
NORN		NST12~			<GD9		<MO9		<GD3		<GD8		<ERR~		<KCE~

-- 13
NANDN		GD12			<ST21~		<FDP~
NANDN		MO4			<ST25~		<OPD~		<PLC
NANDN		MO1		<ST23~		<OPM~		<PLC~
NORN		NST13~			<GD12		<MO4		<MO1

-- 14
NANDN		NST14~			<ST11~		<KPR~

-- 15
-- NANDN		MO2			<ST24~		<OPAS~		
NANDN		MO2			<ST24~		<OPAS~		<TC
NANDN		GD11			<ST21~		<FDP
NORN		NST15~			<MO2		<ST22~		<GD11


-- 21
-- Use buffer to keep both names in display
BUFFER		NST21~			<ST13~

-- 22
NANDN		NST22~			<ST24~		<OPAS~		<TC~

-- 23
NANDN		MO3			<ST24~		<OPD~		<TC~
NANDN		GD16			<ST24~		<OPM~		<NE=10~
NANDN		GD37			<ST25~		<OPM~		<N=0~
NORN		NST23~			<MO3		<GD16		<GD37

-- 24
NANDN		MO7			<ST34~		<KPN		<KPO		<FDPAL~
NORN		NST24~			<MO7		<ST25~

-- 25
NORN		NST25~			<ST23~		<ST31~


-- 31
NANDN		MO5	<ST32~		<OPD~		<FKOP
NANDN		GD24			<MO5		<FDAT~
NORN		GD39			<OPM~		<FKOP~
NANDN		GD22			<ST32~		<GD39
NORN		NST31~			<GD24		<GD22

-- 32
NANDN		GD26			<MO7		<OPMD~
NANDN		MO11			<MO12		<OPD~		<FKOP
NORN		NST32~			<GD26		<MO11

-- 33
NANDN		GD27			<ST34~		<KPN~
NORN		NST33~			<ST14~		<GD9		<GD27

-- 34
NANDN		MO12			<ST35~		<KPO~		<FDP~
NANDN		MO10			<ST35~		<KPN~		<FDPAL
NORN		NST34~			<MO12		<MO10

-- 35
NANDN		GD7			<GD4		<OPMD~
NANDN		MO6			<ST33~		<KPN		<STSUP
NORN		NST35~			<GD7		<ST12~		<MO6


----------------------------------------------------------------------------------------------------------------------------------
-- ERR Flag
----------------------------------------------------------------------------------------------------------------------------------

NANDN		MO22			<GD2		<ØD16		<N1~
NANDN		MO21			<(ST15TC)~	<ØD12~		<SUB		<SNc
NANDN		MO20			<ST24~		<OPM~		<ØD16		<FDAT~		<(R2+TC)~
NANDN		MO19			<ST24~		<OPD~		<ØD0~		<PLC		<BIN~
NANDN		MO18			<ST11+31+33~	<FDAT~		<N1~

NORN		GD125			<MO22		<MO21		<MO20		<MO19		<MO18

NANDN		GD123			<GD125		<ØC

ORN		ERR			<ERR~		<GD123
ORN		ERR~			<ERR		<KC~


----------------------------------------------------------------------------------------------------------------------------------
-- FKOP Flag
----------------------------------------------------------------------------------------------------------------------------------

NANDN		GD140			<ST31~		<OPE~

ORN		FKOP			<FKOP~		<GD140
ORN		FKOP~			<FKOP		<KC~		<KK


----------------------------------------------------------------------------------------------------------------------------------
-- FDPAL Flag
----------------------------------------------------------------------------------------------------------------------------------

	-- *** GLITCH FIX ! ***  ØC added to GD152 to avoid overlapping rise & fall of ØD inputs
NANDN		GD152			<ØDPS~		<DPb~		<ØC
NANDN		GD153			<ØB1~		<ØD0~

ORN		FDPAL			<FDPAL~		<GD152  <POC~	-- Hinweis: POC~ nicht im Schaltplan, Initialisierungshilfe
ORN		FDPAL~			<FDPAL		<GD153


----------------------------------------------------------------------------------------------------------------------------------
-- FDP Flag
----------------------------------------------------------------------------------------------------------------------------------

NANDN		MO25			<ST35		<KPN		<GD153

ORN		FDP			<FDP~		<DPb~   <POC~	-- Hinweis: POC~ nicht im Schaltplan, Initialisierungshilfe
ORN		FDP~			<FDP		<ST12~		<MO25


----------------------------------------------------------------------------------------------------------------------------------
-- FDAT Flag
----------------------------------------------------------------------------------------------------------------------------------

NANDN		MO13			<ST32~		<ØD13~		<(R2+TC)~
NANDN		GD62			<ST11+31+33~	<ØD13~
NANDN		GD75			<ST24~		<PLC~

ORN		FDAT~			<FDAT		<ØD0~
ORN		FDAT			<FDAT~		<MO13		<GD62		<GD75 <POC~	-- Hinweis: POC~ nicht im Schaltplan, Initialisierungshilfe


----------------------------------------------------------------------------------------------------------------------------------
-- PLC Counter
----------------------------------------------------------------------------------------------------------------------------------

-- data

NANDN		GD97			<FKOP~		<PLC~
NANDN		GD96			<ST35		<PLC~
NANDN		GD99			<ST32~		<ØD16~
NANDN		GD98			<ST35~		<ØD16~
NORN		MA5			<GD97		<GD96		<GD99		<GD98

-- clocking

NANDN		GD69			<ST11~		<PLC~
NORN		GD68			<GD69		<ST13~		<MO5
ANDN		GD67			<OPD~		<GD68

NANDN		GD79			<GD67		<ØD0~
NANDN		MO15			<ST25~		<OPM~		<ØD15~
NANDN		MO14			<ST25~		<OPD~		<ØD15~		<FDP
ORN		MO1514			<GD79		<MO15		<MO14

NANDN		GD78			<MO1514		<ØEOD~

-- shift register

SRCT/bits=16	PLC~			d<MA5		c<GD78		t<ØB1~
NOT		PLC			<PLC~


----------------------------------------------------------------------------------------------------------------------------------
-- DPb Counter
----------------------------------------------------------------------------------------------------------------------------------

NANDN		GD127			<ST25~		<PLC~
NANDN		GD115			<ST25~		<OPD~
NORN		MA7			<ST21~		<ST31~		<MO1	<GD127		<GD115
NOT		%UG1.13			<MA7

-- data

NANDN		GD157			<MA7		<ØD0~
ORN		MA9			<ST11~		<ST12~		<ST31~		<GD157

NORN		GD155			<KPD~		<KPO~

NANDN		GD138			<DPb~		<ØD16		<MA9
NANDN		MO26			<ST35~		<GD155		<FDP		<ØD1~
NANDN		GD158			<ST11~		<ØDPS~
NANDN		GD159			<ST31~		<DPa~
NORN		GD136			<GD138		<MO26		<GD158		<GD159

-- clocking

NANDN		MO23			<ST34~		<ØD16~		<FDPAL
NANDN		GD128			<%UG1.13	<ØD13~
ORN		GDMO23.2		<MO23		<GD128

NANDN		GD160			<GDMO23.2	<ØB4~

-- shift register

SRCT/bits=16	DPb~			d<GD136		c<GD160		t<ØB1~


----------------------------------------------------------------------------------------------------------------------------------
-- DPa Counter
----------------------------------------------------------------------------------------------------------------------------------

-- data

NANDN		GD131			<FKOP~		<DPa~
NANDN		GD132			<FKOP		<DPb~
NORN		GD151			<GD131		<GD132

-- clocking

NANDN		GD161			<ØD16		<ØB4~

-- shift register

SRCT/bits=16	DPa~			d<GD151		c<GD161		t<ØB1~


----------------------------------------------------------------------------------------------------------------------------------
-- Leading-Zero Blanking
----------------------------------------------------------------------------------------------------------------------------------

	-- *** GLITCH FIX ! ***  ØT into GD71 changed to ØC to avoid glitch when ØB1 ends, as ØT falls before ØB1~
NANDN		GD71			<ØB1~		<ØC
ORN		FN~			<FN		<GD71
ORN		FN			<FN~		<N1~		<ØD1~		<DPb~

FFDCT/s		DISPON			d<UB6		c<ØEOD~		t<ØT		s<FN
NANDN		GD107			<UB6		<DISPON
NORN		MA4			<GD107		<ST15~		<ST14~		<ST12~		<KPO~		<POC~		<ØD13~

SRCT/bits=16	UB6			d<MA4		c<ØEOD~		t<ØB1~


----------------------------------------------------------------------------------------------------------------------------------
-- Sign a
----------------------------------------------------------------------------------------------------------------------------------

NANDN		GD167			<ST14~		<SNc~
NANDN		MO27			<ST11~		<ØD1~		<SNb~

-- SChaltplan stimmt nicht überein BE
-- KORR: SND/SND~ im Schaltplan (S.11) sind identisch mit SNa/SNa~ (UH2.12/13), keine Inverter.
--       Wieder das RS-Latch der Original-Netzliste.
ORN		SNa			<SNa~		<GD167		<MO27
ORN		SNa~			<SNa		<ST12~		<ST15~		<NST14~		<KC~

----------------------------------------------------------------------------------------------------------------------------------
-- Sign b
----------------------------------------------------------------------------------------------------------------------------------

NANDN		GD184			<ST31~		<SNa~
NANDN		MO32			<ST35~		<FKOP~		<SNb~
ORN		GD183			<GD184		<ST22~		<MO32

NOT		snbKC			<KC~
FFD/+/r		SNb			d<SNb~		k<GD183		r<snbKC


----------------------------------------------------------------------------------------------------------------------------------
-- Sign c
----------------------------------------------------------------------------------------------------------------------------------

NANDN		(ST15TC)~		<ST15~		<TC~
	-- *** GLITCH FIX ! *** ØB8~ & ØC added to GD172 to avoid glitch with ST15 & ØD16	
NANDN		GD172			<(ST15TC)~	<ØD16~		<ØB8~		<ØC
	-- *** PROP LOOP FIX ! *** delay inserted in feedback loop
FFD/+		propFixSNc~		d<SNc~		k<ØC
NANDN		GD174			<CtRecall	<propFixSNc~
ORN		GD173			<GD172		<GD174

NOT		sncPOC			<POC~
FFD/+/r		SNc			d<SNc~		k<GD173		r<sncPOC


----------------------------------------------------------------------------------------------------------------------------------
--  Add/Sub Logic
----------------------------------------------------------------------------------------------------------------------------------

NANDN		MO31			<OPAS~		<OPAM~		<SNa		<SNb~
NANDN		MO30			<OPAS~		<OPAM~		<SNa~		<SNb
NANDN		MO29			<OPAS~		<OPSD~		<SNa		<SNb
NANDN		MO28			<OPAS~		<OPSD~		<SNa~		<SNb~
NORN		SUBSN			<MO31		<MO30		<MO29		<MO28		<OPD~

NANDN		GD166			<ST24~		<SUBSN


NANDN		GD181			<OPES~		<SNb
NANDN		GD180			<OPEA~		<SNb~
NORN		GD179			<GD181		<GD180

NANDN		GD164			<ST15~		<GD179


NORN		SUB~			<GD166		<ST22~		<GD167		<GD164
NOT		SUB			<SUB~


----------------------------------------------------------------------------------------------------------------------------------
-- Register Controls
----------------------------------------------------------------------------------------------------------------------------------

NANDN		GD104			<ST23~		<OPD~
NANDN		GD49			<STAC~		<FKOP
NANDN		GD46			<ST11~		<FKOP
NANDN		GD45			<ST24~		<OPAS~

NORN		CtR1toB			<ST15~		<ST21~		<GD49
NOT		CtR1toR1		<CtR1toB

ORN		CtR2toA			<GD104		<ST24~		<ST22~		<GD49

NORN		CtR2toR2		<GD49		<GD46		<GD45
NOT		CtStoR2			<CtR2toR2

--

NANDN		GD72			<KT~		<ST15~		<OPE~
NANDN		MO16			<KT~		<ST11~		<OPE~		<ERR~
NANDN		CtRecall		<KT~		<ST33~		<KPR~

NOT		CtR1R3toAB		<GD72
-- KORR: POC~ ergänzt laut Schaltplan S.13 (200K an D86/D87): RM wird beim Einschalten gelöscht.
NORN		CtR3toR3		<GD72		<MO16		<CtRecall	<POC~

--

NANDN		GD41			<ST35~		<ØD0~
AND		GD83			<KC~		<ST12~		<GD41		<SUM


----------------------------------------------------------------------------------------------------------------------------------
-- R1 Register
----------------------------------------------------------------------------------------------------------------------------------

-- data

NANDN		GD43			<ST33~		<OPE~

AND		UD1.3			<CtR1toB	<GD83
AND		UD1.11			<CtR1toR1	<GD43		<ØD16~		<R1
OR		R1IN			<UD1.3		<UD1.11

-- clock

NANDN		GD168			<CtR1toB	<%UG1.13
NANDN		GD2			<MO1		<FDP
NORN		UH1.12			<GD168		<ST25~		<GD2

NANDN		GD147			<UH1.12		<ØD16~
ORN		GD145			<MO23		<GD147
NANDN		GMA8.3			<GD145		<ØC

-- register

SRCT/bits=64	R1			d<R1IN		c<GMA8.3	t<ØT


----------------------------------------------------------------------------------------------------------------------------------
-- R2 Register
----------------------------------------------------------------------------------------------------------------------------------

-- data

AND		UD2.6			<CtStoR2	<GD83
AND		UD2.8			<CtR2toR2	<R2
OR		R2IN			<UD2.6		<UD2.8

-- clock

NORN		UB4.3			<CtStoR2	<MO5

NANDN		GD144			<UB4.3		<ØD16~
ORN		GD129			<MO23		<GD144
NANDN		GMA8.4			<GD129		<ØC

-- register

SRCT/bits=64	R2			d<R2IN		c<GMA8.4	t<ØT


----------------------------------------------------------------------------------------------------------------------------------
-- R3 Register
----------------------------------------------------------------------------------------------------------------------------------

-- data

AND		UD3.6			<CtR1R3toAB	<GD83
AND		UD3.8			<CtR3toR3	<R3
OR		R3IN			<UD3.6		<UD3.8

-- clock

ANDN		GD146			<CtR1R3toAB	<ØD16~
NANDN		GMA8.2			<GD146		<ØC

-- register

SRCT/bits=64	R3			d<R3IN		c<GMA8.2	t<ØT


----------------------------------------------------------------------------------------------------------------------------------
-- AU
----------------------------------------------------------------------------------------------------------------------------------

-- A Input

AND		UD2.3			<CtR1R3toAB			<R1
AND		UD2.11			<ST14~		<CtR2toA	<R2
AND		UD3.11			<ST14				<R3
OR		AINR			<UD2.3		<UD2.11		<UD3.11

AND		UD3.3			<ØD16~		<AINR

--

NANDN		GD52			<ØD16~		<ØB8~
NANDN		GD53			<ØD16~		<ØB1~
NORN		GD50			<GD52		<GD53
ANDN		GD48			<ST24~		<TC		<GD50

--

OR		AIN			<UD3.3		<GD48

-- B Input

NANDN		MO24			<ST13~		<OPD~		<PLC

AND		UD1.6			<CtR1toB	<R1
AND		UD1.8			<CtR1R3toAB	<ØD16~		<R3
OR		BINR			<UD1.6		<UD1.8

AND		BIN			<ST14~		<ST22~		<MO24		<BINR

-- C Input

NANDN		GD89			<ØD0~		<ØB1~
AND		CIN			<GD53		<GD89		<BC

-- Clock

ANDN		GD103			<ST25~		<ØD16~
NANDN		GMA8.1			<GD103		<ØC

-----------------------------------------------------------------

-- 1st adder
XOR		RaAB			<AIN		<BIN
XOR		RaSUM			<RaAB		<CIN

AND		RaA•B			<AIN		<BIN
AND		RaA•C			<AIN		<CIN
AND		RaB•C			<BIN		<CIN
OR		RaCry			<RaA•B		<RaA•C		<RaB•C

-- digit register

FFDCT		N8			d<RaSUM		c<GMA8.1	t<ØT
FFDCT		N4			d<N8		c<GMA8.1	t<ØT
FFDCT		N2			d<N4		c<GMA8.1	t<ØT
FFDCT		N1a			d<N2		c<GMA8.1	t<ØT

ANDN		GD109			<ST34~		<KNUM~
OR		N1			<GD109		<N1a

NOT		N1~			<N1

-- normalisation adder with carry

XOR		NaAB			<N1~		<GD59
XOR		NaSUM			<NaAB		<UB5.5

AND		NaA•B			<N1~		<GD59
AND		NaA•C			<N1~		<UB5.5
AND		NaB•C			<GD59		<UB5.5
OR		NaCry			<NaA•B		<NaA•C		<NaB•C

NANDN		GD95			<NaCry		<ØB8
FFDCT		UB5.5			d<GD95		c<ØC		t<ØT

NOT		SUM			<NaSUM

-- ten's carry
OR		GD118			<N8		<N4
AND		GD94			<GD118		<ØB8		<STAC~

AND		UB4.8			<GD94		<RaSUM
OR		CRY			<UB4.8		<RaCry

-- subtraction carry

NOT		BIN~			<BIN
OR		GD88			<BIN~		<AIN

AND		UB4.6			<CRY				<SUB~
AND		UC1.12			<BIN~		<AIN		<SUB
AND		UC1.8			<GD88		<CIN		<SUB
OR		BCIN			<UB4.6		<UC1.12		<UC1.8

-- carry flags

FFDCT		TC			d<BCIN		c<ØEOD~		t<ØT
NOR		(R2+TC)~		<TC		<R2

FFDCT		BC			d<BCIN		c<ØC		t<ØT

-- correction generator

NANDN		GD56			<SUB~		<ØB8~
NANDN		GD92			<SUB		<ØB4~
NORN		GD57			<GD56		<GD92		<ØB2~
NANDN		GD59			<GD57		<TC~

-----------------------------------------------------------------
-- AU misc

NAND		GD120			<RaSUM		<N4
NANDN		NE=10~			<GD120		<N8		<N2

NANDN		N=0~			<N8		<N4		<N2		<N1


--- EOF --------------------------------------------------------------------------------------------------------------------------
